0 – July. 1. Qualification Package. AT89C51ED2. FLASH 8-bit C51 Microcontroller. 64 Kbytes FLASH, 2 Kbytes EEPROM. AT89C51RD2 / AT89C51ED2. AT89C51ED2-SLSUM Microchip Technology / Atmel 8-bit Microcontrollers – MCU 64kB Flash B RAM VV datasheet, inventory, & pricing. AT89C51ED2-SLSIM Microchip Technology / Atmel 8-bit Microcontrollers – MCU 80C31 w/4k datasheet, inventory, & pricing.
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Page 10 NIC P2. Do not try to set this bit. Must be cleared by software. Page 54 Table The status of the Port pins during Power-Down mode is detailed in Table Ordering Information Table Page 90 Figure This is achieved by applying an internal reset to them.
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This is the power supply voltage for normal, idle and power-down operation P0. Symbol Description Symbol Table These inputs are available as alternate function of P1 and allow to exit from idle and power-down modes. The Idle mode and the Power-Down mode. From level 0, one can write level 1 or level 2. Figure gives a logical view of the above statements.
Oscillator To optimize the power consumption and execution time needed for a specific task, an internal prescaler feature has been implemented between the oscillator and the CPU and peripherals. Set to enable a high level datashdet on Port line 7. Set to enable KBF. Page Port 0: Or point us to the URL where the manual is located. Page 12 Table Set by hardware to indicate that the SS pin is at inappropriate logic level.
Set by hardware when an invalid stop bit is detected. The dual DPTR structure is a way by which the chip will specify the address of datasjeet external data memory location. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Document Revision History The programming voltage is internally generated from the standard VCC pin.
CF may be set by either hardware or software but can only be cleared by software. Datasgeet 42 Table It contains 64K bytes of program memory organized respectively in pages of bytes.
Added Flash write programming time specification. Set to enable SPI interrupt.
AT89C51ED2 Datasheet(PDF) – ATMEL Corporation
Page 82 continue for a number of clock cycles before the internal reset algorithm takes control. This can be useful if external peripherals are mapped at addresses already used by the internal XRAM.
Can not be set or cleared by software.
The Kbytes Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. Set to enable timer 2 overflow interrupt. U MOVC instruction executed from external program memory is disabled from fetching datasheeet bytes from internal memory, EA is sampled and latched on reset, and further parallel programming of the on chip code memory is disabled.
It contains a Kbyte Flash memory block for code and for data. Page 74 Table Page 38 Table Your manual failed to upload The WDT is by default disabled from dattasheet reset.